St7920 code example serial#

While(Shift_done_status_Read() != 0) //do nothing until shift completsĬyDelayUs(command_delay) //delay for display processor to complete actionĭisp_control_reg_Write(0b00000000) //should hold stoppedĭata_reg_Write(data_byte) //set up the command byte to send outĭisp_control_reg_Write(0b00000101) //load with register select bit 2 as data 1ĭisp_control_reg_Write(0b00000110) //run,RS x dont care register select in run mode as loaded do nothing a previous shift is in processĭisp_control_reg_Write(0b00000000) //shifting has stopped now, control reg value should hold component stoppedĭata_reg_Write(c_d_byte) //set up the c-d_byte to send outĭisp_control_reg_Write(0b00000001) //load with register select bit 2 as command 0 Uint16 command_delay = 1600 //longest delay used

St7920 code example serial#

should cope with what ever clock is set for the serial component Void ST7920_command_data( uint8 command_data, uint8 c_d_byte)

If (newState = 1) state = 1 else state = 0 // relies on true = 1 and false = 0 Int modifyBit(int x, unsigned char position, bool newState) * END OF FILE */ The C File that will become the API of the Module Void ST7920_write_string(uint8 line, uint8 position ,char *string_out) Void ST7920_write_character(uint8 line, uint8 position ,char character) Now the H file of what will become the API for the module And here is the screen shot of one 24 bit serial frame sent to the display. Had a bit of trouble adding a testbed so below is the screenshot for the the initialising sequence for the display. `#start footer` - edit after this line, do not edit this line Running <= 1’b0 //set up the reg to stop Slave_clock output(always(posedge Clk_in)statement) **************take clock in signal divide by 2 and generate two clocks shifted by 90 degrees************Ī = 1 & count 23)//sent all the serial bits Reg count //set up the incrimenting counter for counting bits shifted `#start body` - edit after this line, do not edit this lineĪssign Ser_out = shifter // set this as the output buffer `#end` - edit above this line, do not edit this line The Verilog HDL that sits inside the component above The Module used in a Creator Schematic design

Only the RS bit (Command or Data) and the 4 Higher and 4 Lower bits of data are going to change in any data frame.

The SPI data that is sent to the display is write only and is made up of 24 bits of data, only 9 bits of data will change in any 24 bit data frame, RW bit (Read/Write) will always be write as there is no read capability in SPI mode. SPI uses 3 but I have opted to add one extra pin to allow for a hardware rest line. There are I2C breakout boards that provide a I2C serial to parallel mode for these displays, which will use only 3 pins from the controller. 4 bit mode will use 8 pins on the controller.So there are a number of options when using this display 4 bit, 8 bit and SPI modes of communication Using programmable hardware to handle what would b a “bit bashing” fest on a micro makes an awful lot of sense to me and being able to do things in parallel without intervention of the embedded micro just seems right. As you will all know by now Crusty of “Crusty Hacks” likes the programmable hardware PSoC chips use. There are lots of Arduino sketches for these types of display, but not much for Cypress PSoC 4 & 5 devices.